The present invention disclosed herein relates to test systems and more particularly, to a test system for a multi-chip package including pluralities of memories (or memory chips).
Many applications are ever demanding improvement of data rate and large capacity of storage. For those requirements, memory manufacturers now drive their fabrication facilities into multi-chip packages (MCPs).
For the purpose of reducing the number of solder balls when pluralities of memory chips are stacked on a printed circuit board (PCB), an MCP is made by assembling the stacked memory chips through common pins thereof by means of a wire-bonding process on the PCB. An increasing number of stacked memory chips or a decreasing number of solder balls reduces the number of branches by wire-bonding. And, while signals transferred to plural chips at the same time diverge through wire-bonded paths, capacitive values existing in plural memory chips become larger to increase a time constant. Therefore, in a test system, there is a problem of deteriorating the integrity of input signals transferred to an MCP in which plural memory chips are stacked.